The present invention relates to CMOS devices and particularly to an electrostatic discharge (ESD) circuit for protecting CMOS devices from positive-going and negative-going high energy electrical transients. More particularly, the present invention relates to an ESD protection circuit which provides protection against large ESD transients and which allows for convenient adjustment of holding current and routing of ESD current through an arbitrary point other than the CMOS substrate.
CMOS devices are commonly used to implement logic functions in electronics applications and in particular, computer applications. Although the use of CMOS devices has become commonplace in the computer industry, there are certain concerns that need to be taken into account in order to ensure proper long-term functioning of components which incorporate these devices. One area of concern in particular relates to the handling of ESD potentials which may be applied to terminals of an integrated circuit containing CMOS devices.
ESD potentials can often be several orders of magnitude larger than signals which would ordinarily be applied to a CMOS device. Indeed, ESD potentials on the order of several kilovolts, even as high as 10 kV, are not uncommon. When such extraordinarily high ESD potentials are applied to a CMOS device, it is not surprising that severe damage to the CMOS device can occur. Typically, the damage to CMOS devices caused by ESD potentials is the result of a breakdown of the oxide layer of the integrated circuit (IC) in the vicinity of the gate of a CMOS device. The breakdown voltage of the oxide layer is a function of its thickness. A general rule of thumb is that conventional oxide in CMOS devices should be able to withstand a potential difference of approximately 70 V per 1,000 .ANG. of oxide layer thickness. For a typical CMOS device with a gate oxide thickness of 500 .ANG., this translates to a maximum "safe" potential difference of about 35 V across the gate oxide. Because ESD potentials applied to a terminal of an integrated circuit can greatly exceed this breakdown voltage, integrated circuits incorporating CMOS devices are at risk of damage if an internal voltage charge is not provided.
One approach that has been taken for providing ESD protection to CMOS devices involves fabricating ESD cells in conjunction with the fabrication of the CMOS devices. Some of these ESD cells form four-layer devices (such as silicon-controlled rectifiers or "SCRs") which transition from a high impedance state to a low impedance state when an ESD potential appears at a terminal of the CMOS IC protected by the ESD cell. In the high impedance state, the ESD cell allows the CMOS devices in the IC to experience normal potentials which are necessary for the CMOS devices to perform their intended function. However, when the potential applied to the protected terminal exceeds a predetermined threshold value (referred to herein as the breakdown voltage of the ESD cell) beyond the normal operating range of the terminal, the ESD cell begins to conduct current, thereby acting as a current source or sink for the current associated with the ESD potential. Such ESD cells are capable of discharging the ESD potential with very little power dissipation, so that not only are the CMOS devices protected, but the ESD cell also goes undamaged.
However, known examples of SCR-based ESD cells such as those described above have not addressed certain difficulties which may present themselves depending upon the intended application for the CMOS devices. For example, the known SCR-based ESD cells route the current associated with the ESD potential to the substrate of the CMOS IC. While this ordinarily has had no adverse effect on the CMOS ICs in which the ESD cells were used, it may nevertheless be undesirable in certain IC designs to direct the current to the CMOS substrate. Indeed, in some IC designs, the substrate may not even be connected to a pin through which the current can be routed. It would therefore be desirable to be able to route the current associated with an ESD potential to an arbitrary point, depending on the needs of a particular application. For many applications, an ideal point would be a circuit path (other than the substrate) electrically connected to an external ground.
An additional drawback relates to the manner which known SCR-based ESD cells are able to discharge the ESD potential without dissipating a significant amount of power. As previously described, an ESD potential exceeding the breakdown voltage of the ESD cell will cause the ESD cell to conduct current. When a threshold level of current flows through the ESD cell, the ESD cell enters a low impedance state which causes the voltage across the four-layered device to rapidly and substantially decline. Since power is the product of voltage and current, the ESD cell is able to discharge the ESD potential without dissipating a significant amount of power by virtue of the fact that the voltage is brought down to extremely low levels. Once the ESD event is over, the ESD cell normally returns to its high impedance state, thereby allowing the protected CMOS devices to experience normal operating potentials.
However, if an external circuit (e.g., a driver) capable of sourcing or sinking a current greater than another threshold level (known as the "holding current") is connected to a protected pin of the CMOS IC at a time when an ESD event occurs, the ESD cell may enter a "quasi-latch-up" condition. When this occurs, the ESD cell fails to reenter its high impedance state following the end of the ESD event, and may prevent CMOS devices in the IC from resuming normal operation. It would therefore be desirable to provide an apparatus for, and a method of fabricating, an ESD cell which allows for adjustment of the holding current on an application specific basis so as to accommodate otherwise normal currents provided by external circuits.